This relates to integrated circuits and, more particularly, to programmable integrated circuits.
Programmable integrated circuits are a type of integrated circuit that can be programmed by a user to implement a desired custom logic function. In a typical scenario, a logic designer uses computer-aided design tools to design a custom logic circuit. When the design process is complete, the computer-aided design tools generate configuration data. The configuration data is loaded into memory elements to configure the devices to perform the functions of the custom logic circuit.
Memory elements are often formed using random-access-memory (RAM) cells. Because the RAM cells are loaded with configuration data during device programming, the RAM cells are sometimes referred to as configuration memory or configuration random-access-memory cells (CRAM). During normal operation of a programmable device, loaded CRAM cells produce static output signals that are applied to the gates of transistors (e.g., pass transistors). The CRAM output signals turn some transistors on and turn other transistors off. This selective activation of certain transistors on the programmable device customizes the operation of the programmable device so that the programmable device performs its intended function.
Configuration data may be supplied to a programmable device in the form of a configuration bit stream. After a first configuration bit stream has been loaded onto a programmable device, the programmable device may be reconfigured by loading a different configuration bit stream in a process known as reconfiguration. An entire set of configuration data is often loaded during reconfiguration. However, it may sometimes be advantageous to reconfigure only a portion of the configuration bits using a process known as partial reconfiguration.
In certain applications, a programmable device includes multiple processing nodes each of which is configured to perform a respective function for a master driver. In a conventional shared bus topology, all the processing nodes are directly connected to the master driver via a high fan-out interface. Although this topology supports partial reconfiguration during which one of the nodes can be reprogrammed without interrupting the rest of the system, the amount of traffic congestion at the fan-out interface is high and can substantially cripple the performance of the system. In another conventional topology, the processing nodes are connected strictly in series. While this arrangement provides high throughput, the latency is dependent on the number of series-connected stages and more importantly, the entire system will collapse if any one of the nodes undergoes partial reconfiguration.
It is within this context that the embodiments herein arise.